The present invention relates generally to semiconductor device manufacturing techniques and, more particularly, to forming improved back gate field effect transistor (FET) devices by using shallow trench isolation (STI) regions to introduce back gate dopant material.
Semiconductor-on-insulator (SOI) devices, such as silicon-on-insulator devices, offer several advantages over more conventional semiconductor devices. For example, SOI devices may have lower power consumption requirements than other types of devices that perform similar tasks. SOI devices may also have lower parasitic capacitances than non-SOI devices. This translates into faster switching times for the resulting circuits. In addition, the phenomenon of latch up, which is often exhibited by complementary metal-oxide semiconductor (CMOS) devices, may be avoided when circuit devices are manufactured using SOI fabrication processes. SOI devices are also less susceptible to the adverse effects of ionizing radiation and, therefore, tend to be more reliable in applications where ionizing radiation may cause operation errors.
On the other hand, SOI devices generally suffer from floating body effects. The body of an SOI FET stores electrical charge as a function of the history of the device, thus changing the body voltage accordingly and becoming a “floating” body. As such, an SOI FET has threshold voltages which are difficult to anticipate and control, and which vary in time. The body charge storage effects result in dynamic sub-threshold voltage (sub-Vt) leakage and threshold voltage (Vt) mismatch among geometrically identical adjacent devices. Floating body effects in an SOI field effect transistor are particularly a concern in static random access memory (SRAM) cells, where Vt matching is extremely important as operating voltages continue to be scaled down.
An evolution beyond the standard FET (which has a single top gate that controls the FET channel) is the double-gated FET, in which the channel is confined between a top and a bottom gate. Positioning the channel between a top gate and a bottom gate allows for control of the channel by the two gates from both sides of the channel, reducing short channel effects. Further, a double-gated FET may exhibit higher transconductance and reduced parasitic capacitance as compared to a single-gated FET. The presence of the back gate allows for enhanced on-chip power management and device tuning. Multiple threshold voltage (Vt) devices may also be achieved on a single IC chip by applying different back biases at the back gates of various devices.